One important requirement for DRAM (Dynamic Random Access Memory) devices is the ability to hold data in an inactive state with the minimum power drain. This power drain comes from the need to refresh the data stored in bit cells in selected portions of the memory, as well as leakage in the rest of the periphery. This specification is referred to as IDD6. This directly affects the usable time from a battery charge for smart phones, laptops, etc. Another important parameter for DRAM devices is latency. Latency is the delay between selecting a random location within the memory device and the arrival of the selected data on the outputs.
One particularly advantageous memory device is set forth in U.S. Pat. No. 7,659,539 to Kreps et al., which is assigned to the present Assignee and hereby incorporated herein in its entirety by reference. This patent discloses a semiconductor device which includes a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.
Despite the advantages of such devices, further developments in memory technology may be desired in certain applications, such as where reduced power drain and latency are desired.